RECENT ASSIGNMENT

Deadline: Finals Week during your lab final
170B Lab Individual Project: Design of a NAND and NOR
During the quarter, you have learned how to design and simulate with PSpice and how to create a layout with Microwind. In this project, you will use such skills to design a larger scale circuit.
Project Requirements:
You are required to design a NAND and NOR gate using PSPICE and Microwind. For your design, you are required to provide the logic gate diagram of your implementation, describe the operation of your circuit and write down I/O relationship by using a truth table.
Design all the gates in your circuit one-by-one with provided truth tables, transistor based schematics, simulations and layouts. Use the model file provided to you, but keep in mind that you need to change the transistor widths for different gates by using the transistor sizing knowledge. For layout, please use the 90nm technology and the same W/L ratio with L=0.1 um that you used in Pspice. Use VPULSE to confirm the logic in Pspice using the following values for input A as V1 and input B as V2. Power supply is 5 V.
After you designed the gates in PSPICE, you have to create the layout in Microwind using L = 0.1 um and W = 0.5 um. Then test the logic using the following inputs.
Project Submission & Grading
In this design project, you will work as an individual. You will submit your PSpice project file and Microwind mask file besides the report that you present all your procedure, results and comments. The report will form the fundamental part of your grade. Also, we will check your participation in the project and understanding of the concepts. In order to do that, you will come to the lab to show your work during your lab final. We will ask you several questions to test your understanding. Therefore, it is better to equally share the project and understand the entire project with more focus in your part.
Design Specifications for both NAND and NOR
Operation Frequency 1GHz
Maximum Layout
Area 100 m2
Power Consumption 100 W
PSpice Model File
This is just a sample model. The widths are given for the inverter. Please change the widths (W) for other gates. Other parameters are fixed all the time.
.model MbreaknSAMPLE NMOS
+W=10e-6?
+L=1e-6?
+VTO=1
+KP=10e-3
+CBD=5pF
+CBS=2pF
+RD=1?
+RS=2
+LAMBDA=0.01
+CGSO=1pF
+CGDO=1pF
+CGBO=5pF
.model MbreakpSAMPLE PMOS
+W=30e-6?
+L=1e-6
+VTO=-1
+KP=3.5e-3
+CBD=5pF
+CBS=2pF
+RD=1?
+RS=2
+LAMBDA=0.01
+CGSO=1pF +CGDO=1pF
+CGBO=1pF